The authors propose a linear systolic array for fast Fourier transform (FFT) computation that is based on the Pease algorithm, which has the advantage of making the systolic array structure uniform from stage to stage. With slight modifications the algorithm can be directly implemented on a systolic array. The array needs only log2
Published in:
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
(Volume:39
,
Issue:
4
)
Date of Publication: Apr 1992