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This paper presents T&D-Bench - teaching and design workbench, a software infrastructure for modeling and simulation of state-of-the-art processors. It combines features that simplify and accelerate the processor design process without restricting the designer possibilities, thus representing a good tradeoff for educational and research purposes that is not found in other environments. In T&D-Bench, a new model is constructed by the designer using script language to define microarchitecture, instruction set, and timing aspects of the processor. These scripts can be produced by a graphical front-end, and a Java simulator targeted at the modeled processor is automatically built from the scripts. This approach can fit well the requirements imposed by the educational environment. Fine-tuning adjustments or the description of more complex processor mechanisms can be achieved by means of modifications in selected parts of the software infrastructure.