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Implementing and evaluating stream applications on the dynamically reconfigurable processor

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13 Author(s)
Suzuki, N. ; Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan ; Kurotaki, S. ; Suzuki, M. ; Kaneko, N.
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Dynamically reconfigurable processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the processing elements(PEs) and distributed memory modules, DRP-1 outperformed pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.

Published in:

Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on

Date of Conference:

20-23 April 2004