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An FPGA implementation for a high throughput adaptive filter using distributed arithmetic

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5 Author(s)
Allred, D.J. ; Georgia Inst. of Technol., Atlanta, GA, USA ; Huang, W. ; Krishnan, V. ; Yoo, Heejong
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In this paper, an FIR adaptive filter implementation using a multiplier-free architecture is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed LMS adaptive filter can be realized employing the proposed architecture.

Published in:

Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on

Date of Conference:

20-23 April 2004