Referenced Items are not available for this document.
The combination of SystemVerilog, SystemC, and the property specification language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs; critical capabilities for these standards include advanced verification features such as solvers and constrained random testing. This combination of standards brings powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.
Published in:
Design & Test of Computers, IEEE
(Volume:21
,
Issue:
6
)
Date of Publication: Nov.-Dec. 2004
- Page(s):
- 592 - 593
- ISSN :
- 0740-7475
- INSPEC Accession Number:
- 8202287
- Digital Object Identifier :
- 10.1109/MDT.2004.98
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 December 2004
- Issue Date :
- Nov.-Dec. 2004
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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