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The combination of SystemVerilog, SystemC, and the property specification language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs; critical capabilities for these standards include advanced verification features such as solvers and constrained random testing. This combination of standards brings powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.
Date of Publication: Nov.-Dec. 2004