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Designing fault-tolerant techniques for SRAM-based FPGAs

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5 Author(s)
de Lima Kastensmidt, F.G. ; Dept. of Digital Syst. Eng., State Univ. of Rio Grande do Sul, Guaiba, Brazil ; Neuberger, G. ; Hentschke, R.F. ; Carro, L.
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FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.

Published in:

Design & Test of Computers, IEEE  (Volume:21 ,  Issue: 6 )