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Enhanced equivalence checking: toward a solidarity of functional verification and manufacturing test generation

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3 Author(s)

This article, from the Motorola (now Freescale) PowerPC design group, presents an interesting synergy among test, equivalence verification, and constraints. The authors use RTL, gate, and switch models of a design in two different flows one for test and one for functional verification to show that rectifying constraints and merging tests between the-two flows saves significant presilicon debug effort.

Published in:

Design & Test of Computers, IEEE  (Volume:21 ,  Issue: 6 )

Date of Publication:

Nov.-Dec. 2004

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