Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

A layered adaptive verification platform for simulation, test, and emulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

This adaptive architecture for structuring testbenches accommodates various models of a design, from transaction to silicon. Moreover, the adapter-based architecture supports the execution of design models on different simulators (high level, RTL, gate level, and switch level), hardware emulators (the testbench runs entirely on the emulator), and even testers. Here, we present a modular, layered testbench (MLTB) approach to building a testbench. This approach is similar to platform-based design. It consists of a generic testbench kernel (TBK), connected through a bus to testbench elements. Our verification platform also satisfies another meaning of platform: a set of connected tools or a powerful tool environment, normally with an attached database, that acts as a platform for verification.

Published in:

Design & Test of Computers, IEEE  (Volume:21 ,  Issue: 6 )