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This paper reports on the progress toward implementing optical-digital building blocks necessary to accomplish a system-on-package module architecture for high-performance multiprocessors. In this architecture, the memory access delay (MAD) bottleneck is minimized by using a 3-D distributed shared memory field in which high speed optical interconnects deliver data to and from each processor in a cluster to each memory controller/MX-DMX in the field, each memory controller being connected to a small cluster of main memory via a short, high aggregate speed copper bus that essentially matches the intrinsic MAD of the DRAM chip.
Lasers and Electro-Optics Society, 2004. LEOS 2004. The 17th Annual Meeting of the IEEE (Volume:2 )
Date of Conference: 7-11 Nov. 2004