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SOI flash memory scaling limit and design consideration based on 2-D analytical modeling

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6 Author(s)
A. C. K. Chan ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China ; Tsz-Yin Man ; Jin He ; Kam-Hung Yuen
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In this paper, the short-channel effect in ultrathin body (UTB) SOI Flash memory cell induced by the floating-gate is investigated by a newly developed two-dimensional analytical model. A concept of effective natural length (λeff) is introduced as a measure of the impact of the floating-gate on the scaling limit. Even though scaling the channel thickness can significantly reduce SCE in UTB MOSFET, it becomes less effective in floating-gate device due to the floating polysilicon induced gate coupling. To minimize the floating-gate induced SCEs, the drain to floating-gate coupling has to be minimized.

Published in:

IEEE Transactions on Electron Devices  (Volume:51 ,  Issue: 12 )