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40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology

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2 Author(s)
Galal, S. ; Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA ; Razavi, B.

A triple-resonance LC network increases the bandwidth of cascaded differential pairs by a factor of 2√3, yielding a 40-Gb/s CMOS amplifier with a gain of 15 dB and a power dissipation of 190 mW from a 2.2-V supply. An ESD protection circuit employs negative capacitance along with T-coils and pn junctions to operate at 40 Gb/s while tolerating 700-800 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 12 )