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Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate

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2 Author(s)
Larrieu, Guilhem ; IEMN/ISEN UMR CNRS, Villeneuve d''Ascq, France ; Dubois, E.

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO2-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of Ion/Ioff without any sign of sublinear upward bending of the IDS--VDS curves at low drain voltage.

Published in:

Electron Device Letters, IEEE  (Volume:25 ,  Issue: 12 )

Date of Publication:

Dec. 2004

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