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Generation of test patterns without prohibited pattern set

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3 Author(s)
Sikdar, B.K. ; Dept. of Comput. Sci. & Technol., Bengal Eng. Coll., Howrah, India ; Ganguly, N. ; Pal Chaudhuri, P.

This work reports the design of a fool proof on-chip test pattern generator (TPG) for very large scale integration circuits. The TPG is designed to generate pseudorandom test patterns without a given prohibited pattern set (PPS). It ensures desired pseudorandom quality of the generated test patterns and maintains fault coverage close to the figures achieved with a conventional maximal length linear feedback shift register/cellular automaton (CA)-based TPG. The theory of vector subspace generated by a CA (Chaudhuri, 1997) has provided the foundation of this design. The proposed TPG does not incur any additional cost for the avoidance of PPS.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:23 ,  Issue: 12 )