Referenced Items are not available for this document.
This paper proposes a dynamic delayed line bus scheme (DDL) for low-power on-chip buses. This scheme dynamically introduces a delay to bus lines having a certain switching activity to create relative delay between opposite switching adjacent lines. The optimum relative delay introduced by this proposed scheme is shown to reduce the power dissipation by up to 16%.
Published in:
SOC Conference, 2004. Proceedings. IEEE International
Date of Conference: 12-15 Sept. 2004
- Page(s):
- 233 - 236
- Print ISBN:
- 0-7803-8445-8
- INSPEC Accession Number:
- 8169720
- Digital Object Identifier :
- 10.1109/SOCC.2004.1362419
- Product Type:
- Conference Publications
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