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New mixed analog/digital PRML (partial response maximum likelihood) architecture for the optical drive system is presented. In order to realize high speed, low power and low cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits to provide high speed and low power data detection for optical data storage system. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and area by 42%, therefore it provides high speed, low power and low cost SOC solution for the future optical drive system. A test chip produced is fabricated using 0.18 μm CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.