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An embedded read only memory architecture with a complementary and two interchangeable power/performance design points

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1 Author(s)
S. Eustis ; IBM Microelectron., Essex Junction, VT, USA

This paper focuses on the features of a 0.13 μm embedded, compilable read only memory (ROM). A complementary array cell is described which increases and maintains signal margins across array sizes despite the ever-increasing capacitive coupling effects and lower voltages of each succeeding technology generation. A new architecture is described which allows a customer to switch between two different power/performance design points while only changing the metal wiring in the ROM via a compiler. Hardware data is presented which illustrates the success of the array design and difference between the two power/performance design points.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004