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This paper presents an interface technique for hazard-free communication among synchronous intellectual property (IP) cores that belong to different clock domains. By allowing each IP core to run at its most efficient operating point, the proposed interface can yield significant power reductions in synchronous system-on-chip (SoC) designs. The technique is probably correct and achieves maximum throughput when transferring data across long distances. Its performance has been assessed through Hspice simulations.