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Reducing crosstalk noise in high speed FPGAs

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1 Author(s)
A. Mukherjee ; Dept. of ECE, UNC, Charlotte, NC, USA

Narrowing time-to-market windows are driving the design community toward FPGAs. Whereas quick prototype implementations are possible using FPGAs, circuit delays have always been a major concern. Moreover, achieving high performance in FPGAs with densely packed routing resources is difficult because of crosstalk noise. In this paper we describe a very high performance FPGA, and show a simple and practical technique of almost reducing crosstalk noise by using a two-phase nonoverlapping complimentary clocking scheme. An efficient integer linear programming formulation has been proposed to find an optimum solution to a constrained problem, and we have studied the effects and costs of applying our idea to different architectures. Experiments with MCNC benchmark circuits in different architectures of our FPGA show that, on average, we could reduce crosstalk induced delay increases to less than 4% of the clock period. With a minimal increase of 3% in area due to this optimization, our results seem very promising.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004