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This paper presents the implementation of high throughput and low power FIR filtering IP cores. Multiple datapaths are utilized for high throughput and low power is achieved through coefficient segmentation, block processing and combined segmentation and block processing algorithms. The paper presents the complete architectural implementation of these algorithms for high performance applications. The paper describes the design methodology, evaluation environment, and provides results which show up to 33% reduction in power consumption with less than 10% increase in area depending on the number of datapaths.