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Leakage aware SER reduction technique for UDSM logic circuits

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4 Author(s)
P. Elakkumanan ; Dept. of Comput. Sci. & Eng., Buffalo Univ., NY, USA ; V. Ananthakrishnan ; A. Narasimhan ; R. Sridhar

With technology scaling aggressively into the very deep submicron era, leakage power and single event upsets (SEUs) pose serious challenges to circuit designers. Here, we present a technique to reduce the soft error rate (SER) in combinational circuits, with minimal area overhead using minimum leakage input vector (MLIV) leakage reduction technique. Simulation results show significant reduction in area overhead as compared to existing techniques, while reducing the leakage power by nearly 40%.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004