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As the number of global interconnect buffers is expected to reach 700,000 in the 70nm CMOS process, their adverse impact on the chip total power consumption becomes evident. In this paper, we formulate the power optimal maze routing and buffer insertion/sizing problem for a two pin net, as a shortest paths ranking problem. The polynomial time bound on our formulation fits well within the context of the increased number of buffers. Moreover, its ability to account for buffer and wire blockage arising from the underlying blocks in today's SOC's is an advantage over the analytical alternative formulations. During the assessment of the impact of technology scaling using a set of MCNC benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.