By Topic

Fast techniques for standby leakage reduction in MTCMOS circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wenxin Wang ; Sch. of Eng., Guelph Univ., Ont., Canada ; M. Anis ; S. Areibi

Technology scaling causes subthreshold leakage currents to increase exponentially. Therefore, effective leakage minimization techniques must be designed. In addition, for a true low-power solution in system-on-chip (SoC) design, it has to be tightly integrated into the main design environment. This paper presents two design techniques to effectively solve the sleep transistor sizing and distribution problem in MTCMOS circuits. The introduced first-fit and set-covering approaches achieve lower leakage at an order of magnitude reduction in CPU time compared with other techniques in the literature. In addition, an automatic MTCMOS design environment is developed and integrated into the Canadian Microelectronics Corporation (CMC) digital ASIC design flow.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004