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Technology scaling causes subthreshold leakage currents to increase exponentially. Therefore, effective leakage minimization techniques must be designed. In addition, for a true low-power solution in system-on-chip (SoC) design, it has to be tightly integrated into the main design environment. This paper presents two design techniques to effectively solve the sleep transistor sizing and distribution problem in MTCMOS circuits. The introduced first-fit and set-covering approaches achieve lower leakage at an order of magnitude reduction in CPU time compared with other techniques in the literature. In addition, an automatic MTCMOS design environment is developed and integrated into the Canadian Microelectronics Corporation (CMC) digital ASIC design flow.