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Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications

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3 Author(s)
Becker, L.B. ; Comput. Sci. Inst., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil ; Wehrmeister, M.A. ; Pereira, C.E.

This paper evaluates how distinct real-time task scheduling algorithms impact power consumption and timing performance of embedded systems. A design space exploration methodology is proposed in order to adjust the system's power consumption by tuning the CPU frequency according to the scheduling algorithm and to the temporal requirements of the embedded application. The goal is to find an optimized configuration, selecting the right combination of a scheduling policy with a CPU frequency, so as to consume less power without missing any deadline in the application. Experiments based on a synthetic workload that simulates realistic applications demonstrate that considerable power savings can be obtained. Moreover, the paper defines guidelines to be used by system designers in order to find a configuration that best matches the design constraints and requirements.

Published in:

Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on

Date of Conference:

7-11 Sept. 2004