By Topic

Fast exploration of bus-based on-chip communication architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
S. Pasricha ; Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA ; N. Dutt ; M. Ben-Romdhane

As a result of improvements in process technology, more and more components are being integrated into a single system-on-chip (SoC) design. Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks. It therefore becomes extremely important for designers to explore the communication space early in the design flow. Traditionally, pin-accurate bus cycle accurate (PA-BCA) models were used for exploring the communication space. To speed up simulation, transaction based bus cycle accurate (T-BCA) models have been proposed, which borrow concepts found in the transaction level modeling (TLM) domain. The cycle count accurate at transaction boundaries (CCATB) modeling abstraction was introduced for fast communication space exploration. In This work, we describe the mechanisms that produce the speedup in CCATB models and demonstrate the effectiveness of the CCATB exploration approach with the aid of a case study involving an AMBA 2.0 based SoC subsystem used in the multimedia application domain. We also analyze how the achieved simulation speedup scales with design complexity and show that SoC designs modeled at the CCATB level simulate 120% faster than PA-BCA and 67% faster than T-BCA models on average.

Published in:

Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. International Conference on

Date of Conference:

8-10 Sept. 2004