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Globally asynchronous locally synchronous (GALS) design style has evolved as a solution to increasing problems of distributing clock at high frequency in DSM technology. Most wrapper designs proposed in some recent literature are based on bundled data protocols and suffer from the same timing closure problem as synchronous designs. Delay insensitive (DI) protocols offer a solution to this problem. However, most of the work on DI schemes was limited to asynchronous circuits so far. This is, to our knowledge, the first paper that presents a complete asynchronous wrapper architecture for GALS designs based on a DI protocol. It uses 1-of-4 data encoding with single-track handshaking. The resulting circuit shows a throughput of 1.66 Gbps, significantly higher than previous asynchronous DI templates.