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This paper presents an approach to convert synchronous circuits to asynchronous circuits. The global clock network is replaced by asynchronous control circuits. Meanwhile, the combination logic in datapath stays eventually the same. We choose GasP circuits to implement the asynchronous control logic and we adopt a doubly latched scheme in datapath, using modified dynamic master-slave DFFs [Ra96] to replace original registers in synchronous circuits. Case studies of the conversion method prove that our approach is feasible. The resulting circuits show a speed advantage over the original synchronous design. Hspice simulation results show that the cycle time of a four-bit LFSR after conversion is 1.83 ns while the cycle time of the original LFSR is 1.99 ns.