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Reconfigurable systems now offer tens of millions equivalent gates, allowing highly parallel processing impossible to reach with general purpose processors. Nevertheless, designing a circuit is intrinsically more complicated than a software approach because space and time concepts must be considered together. Current HDLs, which use a low level description, are only accessible to highly qualified hardware designers and require much more time than a pure software solution. This paper demonstrates how the use of higher level HDL allows people with a software background to design complex architectures in a simple and an efficient way. Five sort algorithms have been designed and tested in a few days using our intermediate level HDL. Results show that the design time, circuit space and global performances are at least one order of magnitude better than a processor approach for a NoC and could easily go to three orders of magnitude.