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SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories

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8 Author(s)
Ishii, Tomoyuki ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Osabe, T. ; Mine, T. ; Sano, T.
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This work presents a gain-cell solution in which a novel ultrathin poly-silicon film transistor provides the basis for dense and low-power embedded random-access memory. This is made possible by the 2-nm-thick channel of the new transistor (single-electron shut off transistor, or SESO transistor), which realizes a quantum-confinement effect that produces a low leakage current value of only 10-19 A at room temperature. Combining with vertical SESO structure, 3T gain cell achieves 1/3 the cell area of SRAM. Using circuit techniques, power consumption of SESO memory is expected to be lower than SRAM. The memory has potential to solve the power and stability problem that SRAM is going to face in the near future.

Published in:

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Date of Conference:

3-6 Oct. 2004