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A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface

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12 Author(s)
Tyhach, J. ; Altera Corp., San Jose, CA, USA ; Wang, B. ; Chiakang Sung ; Huang, J.
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As FPGAs become more integrated into high-speed systems, high performance I/O with excellent signal integrity becomes more important. This paper describes how these challenges were met on an FPGA developed to support 1.6 Gbps differential source-synchronous standards and 300 MHz external memory interfaces. The I/O buffer features programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3v tolerance. High-speed performance was achieved using design techniques of differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. In addition, DLLs and programmable phase offset circuits were used to obtain precise timing control. The chip was manufactured on a 90 nm CMOS process.

Published in:

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Date of Conference:

3-6 Oct. 2004