Design and implementation of an embedded 512KB level 2 cache subsystem

Dual on-chip 512 kB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13 /spl mu/m technology. Each 512 kB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 13 V and 85 C. This fully integrated subsystem is composed of data and tag SRAMs along with datapaths, controller and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64b microprocessors, with a data latency of only 4 cycles including ECC correction for 128-bit data. The design solutions to build this integrated short latency L2 cache are discussed.