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Design and implementation of an embedded 512KB level 2 cache subsystem

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11 Author(s)
Shin, J.L. ; Sun Microsystems Inc., Sunnyvale, CA, USA ; Petrick, B. ; Levy, H. ; Jinseung Son
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Dual on-chip 512 kB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13 μm technology. Each 512 kB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 13 V and 85 C. This fully integrated subsystem is composed of data and tag SRAMs along with datapaths, controller and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64b microprocessors, with a data latency of only 4 cycles including ECC correction for 128-bit data. The design solutions to build this integrated short latency L2 cache are discussed.

Published in:

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Date of Conference:

3-6 Oct. 2004