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This paper reports a multiple integration method for providing a greatly improved signal-to-noise ratio for high resolution infrared focal plane array (FPA) applications. In this method, the signal from each pixel is repeatedly sampled into the integration capacitor, and then outputted and summed into outside memory, continuing for n read cycles during the period of a frame, so that the effective charge integration capacity is increased and the sensitivity is improved. It requires a low noise function block and high speed operation of the readout circuit, so a new concept of readout circuit, performing digitization by the voltage skimming method, is proposed. The readout circuit has been fabricated using a 0.6 μm CMOS process for a 64×64 mid-wavelength infrared (MWIR) HgCdTe detector array. It has been found that the readout circuit can effectively increase the charge storage capacity up to 2.4×108 electrons, and then provides a greatly improved signal-to-noise ratio by approximately a factor of 3.