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A 3D mixed-mode ESD protection circuit simulation-design methodology

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6 Author(s)
H. Xie ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; R. Zhan ; H. Feng ; G. Chen
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Electrostatic discharge (ESD) is a serious IC reliability problem. On-chip ESD protection is used to protect ICs against ESD damage. This paper presents a real 3D mixed-mode ESD protection circuit simulation-design methodology for ESD design prediction. Practical ESD protection design examples in 0.35 μm BiCMOS are given.

Published in:

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Date of Conference:

3-6 Oct. 2004