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This work describes the design of asynchronous sigma delta modulators (ASDMs) with a binary quantizer with hysteresis. The ASDM is treated as a closed loop non-linear system that operates using an inherent limit cycle. A first and a second order ASDM have been implemented in a digital 0.18 μm CMOS technology. The measured SFDR is 75 dB in a frequency band of 8 MHz for the first-order and 72 dB in a band of 12 MHz for the second-order ASDM.