Design and performance of the low noise cascode IC for wireless applications

The paper presents the design and test results of a novel low noise cascade amplifier IC for applications in the GSM and WCDMA base station receivers. The selection of transistor geometry to minimize noise figure and the factors affecting the intermodulation properties are discussed. Stability of the cascade circuit and the interaction with the package is examined and the guidelines for optimum design are formulated. The resulting CGY2J07 dual cascade chip manufactured by OMMIC demonstrates minimum noise figure NFmin = 0.35 dB in the 2 GHz band and in a balanced amplifier configuration provides > 23 dB gain with the input IP3 value of 9 dBm and NF below 0.7 dB. This is the only chip currently available on the market with this level of performance.