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Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM

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4 Author(s)
Chunseok Jeong ; Div. of Electr. & Comput. Eng., Hanyang Univ., Seoul, South Korea ; Changsik Yoo ; Jae-Jin Lee ; Joongsik Kih

A digital delay locked loop (DLL) for 1.2 Gb/s/pin double data rate (DDR) SDRAM is described, which incorporates duty cycle correction (DCC). The DCC locking information is also stored as a digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL, implemented in a 0.35 μm CMOS technology, provides an output clock with 64 ps peak-to-peak jitter and the accuracy of the DCC is ±0.7% for ±10% input duty error from 250 MHz to 600 MHz clock frequency. The digital DLL, excluding I/O buffers, dissipates 10 mW from a 2.5 V power supply.

Published in:

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Date of Conference:

21-23 Sept. 2004