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Assessment of the merits of CMOS technology scaling for analog circuit design

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2 Author(s)
Vertregt, M. ; Philips Res., Eindhoven, Netherlands ; Scholtens, P.C.S.

Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications for an analog-to-digital converter building block are estimated. Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes.

Published in:

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Date of Conference:

21-23 Sept. 2004