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We have realized a 46F2 SRAM cell size of 0.294 μm2 with 80 nm technology and single stack S3 cell technology. SSTFTs and vertical node contacts are major keys in the S3 cell technology. The stacked single crystal silicon thin film is developed for the load pMOS SSTFT of the S3 SRAM cell. The load pMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64 Mbit SRAM is achieved by this S3 cell technology. The basic reliability of SSTFT, with 80 nm length, is also investigated in this study.