Referenced Items are not available for this document.
Design techniques for a low-power pipelined analog-to-digital converters (ADC) without using a front-end sample-and-hold amplifier are presented. Two sampling topologies are compared that minimize aperture error by matching the time constant between signal paths. A digital correction expansion technique is also presented for multibit ADCs, which further increases tolerance to aperture error. Elimination of the front-end SHA can save more than half of the ADCs static power dissipation.
Published in:
Circuits and Systems I: Regular Papers, IEEE Transactions on
(Volume:51
,
Issue:
11
)
Date of Publication: Nov. 2004
- Page(s):
- 2123 - 2132
- ISSN :
- 1549-8328
- INSPEC Accession Number:
- 8241519
- Digital Object Identifier :
- 10.1109/TCSI.2004.836842
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 15 November 2004
- Issue Date :
- Nov. 2004
- Sponsored by :
- IEEE Circuits and Systems Society
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