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The implementation of a low-voltage zero-voltage-switching quasi-square-wave (ZVS-QSW) buck converter capable of meeting the future challenges of low-voltage VRMs is presented. By eliminating switching losses, high-efficiency operation at switching frequencies beyond 1 MHz is achieved. The design uses novel high-speed dead-time-locked-loops with fast dead-time error rejection to ensure zero-voltage-switching under dynamic loads and variable output conditions. The ZVS-QSW converter, which was implemented in a mixed-signal 0.18 m CMOS process, has a measured efficiency of 82% at 5 MHz with a 1.4 V output. The ZVS-QSW converter is intended to supply the next generation VLSI chips with a variable supply voltage for dynamic voltage scaling (DVS) applications. DVS refers to the real-time scaling of the supply voltage to the VLSI chip to minimize dynamic power consumption, while satisfying a variable target clock frequency. Several DVS strategies are examined, and it is shown that DVS can be applied to the ZVS-QSW converter using a dual-mode configuration. An experimental DVS test-bench was developed using a state-of-the-art Xilinx CPLD capable of operating from 1.35 V to 1.8 V. The PID controlled DVS system achieves the maximum VDD transition in 22 μs.
Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual (Volume:6 )
Date of Conference: 20-25 June 2004