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Randomized parallel schedulers for switch-memory-switch routers: analysis and numerical studies

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3 Author(s)
Prakash, A. ; Texas Univ., Austin, TX ; Aziz, A. ; Ramachandran, V.

We present new results and numerical studies of very fast schedulers for SMS (switch-memory-switch) routers, which emulate output-queuing by buffering packets in a partitioned shared-memory located between input and output ports. The architecture of Juniper's core routers and Brocade's storage switches is based on SMS. Our numerical results demonstrate that RiPSS, a randomized highly parallel SMS scheduler that we had developed recently, runs in just 3 rounds on switches with up to 4,096 inputs, and has a very low drop probability. We also show that RiPSS makes effective use of the shared-memory, with packets being uniformly distributed across the memory hanks for both Bernoulli and bursty arrivals. We describe a new and improved randomized pipelined scheduler, PRiPSS, and analyze its performance. Both our analysis and our simulation results for PRiPSS show that it has better throughput than RiPSS with a slightly higher latency in terms of rounds of communication in the underlying hardware. Our analysis also shows that PRiPSS is self-stabilizing, i.e., if occasional lapses occur due to the probabilistic nature of the algorithm, it resumes normal behavior without the need for external intervention. While the choice of RiPSS or PRiPSS would depend on whether throughput or latency is the primary concern, our results indicate that both schedulers are much faster than other schedulers for output-queuing, whether implemented directly or through emulation on SMS

Published in:

INFOCOM 2004. Twenty-third AnnualJoint Conference of the IEEE Computer and Communications Societies  (Volume:3 )

Date of Conference:

7-11 March 2004