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Low-power and high-speed architecture for EBCOT block in JPEG2000 system

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2 Author(s)
R. E. Aly ; Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA ; M. A. Bayoumi

In this paper we propose a novel low power and high-speed architecture for the context formation sub block in tier-1 block of JPEG2000 system. The proposed architecture is inspired from the statistical analysis results on 20 images with 512*512 bits each. The behavior of the proposed architecture is compared to the speedy architecture proposed. For code block size of 64*64 bits, the timing and power consumption analysis show that the proposed architecture can reduce the power consumption by approximately 21% and increase the processing speed by approximately 46% with respect to the reference architecture.

Published in:

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on  (Volume:3 )

Date of Conference:

25-28 July 2004