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Clock synchronization errors in circuits: models, stability and fault detection

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2 Author(s)
C. Lorand ; Dept. of Electr. Eng., Notre Dame Univ., IN, USA ; P. H. Bauer

This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fault detection and identification methods for this type of system are provided, by using a state-space approach to asynchronously switching systems.

Published in:

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on  (Volume:2 )

Date of Conference:

25-28 July 2004