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We present a massively parallel VLSI realization of a pulse-coupled neural network for image segmentation. The network comprises 128 × 128 simple nonleaky integrate-and-fire (IAF) neurons with self-organizing inter-neural connections. The prototype implementation also contains analog memories for image storing and a digital readout circuit using an address-event-representation (AER) protocol. The chip has been designed in an Infineon 0.13 μm standard CMOS technology.