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Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access

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3 Author(s)
Hariyama, M. ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; Sasaki, H. ; Kameyama, M.

This paper presents a VLSI processor for high- speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.

Published in:

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on  (Volume:2 )

Date of Conference:

25-28 July 2004

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