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Array hybrid multiplier versus modified booth multiplier: comparing area and power consumption of layout implementations of signed radix-4 architectures

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5 Author(s)
de Oliveira, L.L. ; UFSM/PPGEE, Santa Maria, Brazil ; Costa, E. ; Bampi, S. ; Baptista, J.
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In this paper, we describe the fully automated custom layout implementations of two architectures for signed multiplication. Performance comparisons between the two, namely in terms of their power consumption and area estimation are provided for 8 and 16-bit operands. The first architecture consists of a signed array multiplier that uses a radix-4 hybrid encoding to reduce the partial product lines and switching activity in the data buses. This new arithmetic operand encoding was recently proposed in (Costa et al., 2004), however only results at the logic level were presented. The second architecture implemented was the widely used modified Booth multiplier (Khater et al., 1996). The layout of both multipliers was generated by an automatic layout synthesis tool called TROPIC (MOraes, 1999). We compare the layout implementations in terms of area and power, as well as provide comparisons to first-order area estimates done in the logic design phase. The results show that the new hybrid array multiplier can be significantly more efficient, with close to 30% power savings.

Published in:

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on  (Volume:2 )

Date of Conference:

25-28 July 2004