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A dual transmission gate adiabatic logic (DTGAL) suitable for driving large capacitance is presented. DTGAL, has no non-adiabatic energy loss on output loads by using feedback control from next-stage buffer outputs. The minimization of energy consumption was investigated by choosing the optimal size of DTGAL circuits. A 64×64-b adiabatic SRAM is designed. The proposed DTGAL circuits are used to recover the charge of large switching capacitance on bit-lines, word-lines, and address decoders in fully adiabatic manner. The power consumption of the proposed SRAM is significantly reduced as the energy transferred to large capacitance buses is mostly recovered. Energy and functional simulations were performed using the net-list extracted from the layout. HSPICE simulation results indicate that the proposed SRAM attains energy savings of 65% to 90% as compared with the conventional CMOS implementation for clock rates ranging from 25 to 200 MHz.