Skip to Main Content
Accounting for the effects of inductive, resistive as well as capacitive parasitics of interconnects and on-chip inductors is essential to the success of parasitic-aware RF circuit synthesis at high frequencies. This paper presents an approach for RF circuit synthesis, based on fast procedural layout generation and extraction of all parasitics using multiple extractors. While the parasitic capacitances are obtained using standard rule-based techniques, parasitic resistances and inductances are computed using a fast, yet accurate quasi-static inductance extraction method. Both self and mutual inductances and resistances of inductors and interconnects, which play a significant role at high frequencies, are accounted in the process. A simulated-annealing based optimization algorithm controls design space exploration. Synthesis results show that the proposed methodology yields designs that are more realistic and accurate compared to approaches that ignore resistive and inductive parasitics of interconnects.