Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning

Based on the analysis of optimal wire width on one wire segment, the wire planning with optimal wire widths is proposed to use less routing area to reduce the timing delay of any interconnection net. Furthermore, given one compacted floorplan with a set of interconnection nets, based on the analysis of buffer locations on one wire segment and the construction of a recursive buffer-location graph, an area-driven buffer block planning with optimal wire sizing (ABBP/spl I.bar/OWS) algorithm is proposed to insert the feasible buffers into the given floorplan for each net without destroying the timing constraint of any routing net. Finally, the experimental results show that the proposed ABBP/spl I.bar/OWS algorithm increases less routing area and floorplan area to meet more interconnection nets on all the tested benchmark circuits for interconnect-driven floorplanning.