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Design techniques for a CMOS low-power low-voltage fully differential flash analog-to-digital converter

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3 Author(s)
Tsung-Sum Lee ; Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan ; Li-Dyi Luo ; Chin-Sheng Lin

A CMOS 8-bit, 33.3 MS/s flash ADC with ±1.5 V power supply is developed through the use of a CMOS low-power high-speed fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than ±0.3 LSB. Signal-to-(noise and distortion) ratio is 46.2 dB at a sampling rate of 33.3 MS/s and input frequency of 4 MHz. The power dissipation is 106 mW at 33.3 MS/s with ±1.5 V power supply.

Published in:

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on  (Volume:1 )

Date of Conference:

25-28 July 2004