Design techniques for a CMOS low-power low-voltage fully differential flash analog-to-digital converter

A CMOS 8-bit, 33.3 MS/s flash ADC with /spl plusmn/1.5 V power supply is developed through the use of a CMOS low-power high-speed fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than /spl plusmn/0.3 LSB. Signal-to-(noise and distortion) ratio is 46.2 dB at a sampling rate of 33.3 MS/s and input frequency of 4 MHz. The power dissipation is 106 mW at 33.3 MS/s with /spl plusmn/1.5 V power supply.